FEATURES

• Can be driven on 5 V (Dynamic range: 4.6 V, VDD2 = 5.0 V)

• 300/288-output

• fCLK = 15 MHz MAX. (VDD1 = 3.0 V)

• Simultaneous/sequential sampling selectable according to pixel array

Simultaneous sampling: Vertical stripe

Sequential sampling: Vertical stripe, delta array, mosaic array

• Two sets of sample and hold circuits

• Stripe, delta, and mosaic pixel arrays supported by internal multiplexer circuit

• Left and right shift selected by R,/L pin

• COG mounting possible