FEATURES

• CMOS level input (2.3 V to 3.6 V)

• 384 Outputs

• Input of 6 bits (gradation data) by 6 dots

• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and

a D/A converter (R-DAC)

• High-speed data transfer: fMAX. = 65 MHz (internal data transfer speed when operating at VDD1 = 3.0 V)

• Output dynamic range VSS2 + 0.1 V to VDD2 – 0.1 V

• Apply for dot-line inversion, n-line inversion and column line inversion

• Output Voltage polarity inversion function (POL)

• Display data inversion function (POL2)

• Low power control function (LPC)

• Logic power supply voltage (VDD1) : 2.3 V to 3.6 V

• Driver power supply voltage (VDD2) : 8.5 ± 0.5 V

• Different point between m PD16732A, 16732B : The ladder resistors value(Refer to 5. RELATIONSHIP

BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE)