▪ Six independent timing channels

• Each can act as a frequency synthesizer, jitter attenuator,

Digitally Controlled Oscillator (DCO), or Digital Phase Lock Loop (DPLL)

• Generates output frequencies that are independent of input

frequencies via a Fractional Output Divider (FOD)

• Each FOD supports output phase tuning with 1ps

▪ 12 differential / 24 LVCMOS outputs

• Any frequency from 0.5Hz to 1GHz (250MHz for LVCMOS)

• Jitter below 150fs RMS (10kHz to 20MHz)

• Supports LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL,

and HSTL output modes

• Differential output swing is selectable: 400mV / 650mV /

800mV / 910mV

• Independent output voltages of 3.3V, 2.5V, or 1.8V

▪ LVCMOS additionally supports 1.5V or 1.2V swings

• The clock phase of each output is individually programmable

in 1ns to 2ns steps with a total range of ±180°

▪ 5 differential / 10 single-ended clock inputs

• Supports any frequency from 0.5Hz to 1GHz

• Any input can be mapped to any or all of the timing channels

• Redundant inputs frequency independent of each other

• Any input can be designated as external frame/sync pulse of

EPPS (even pulse per second), 1PPS (Pulse per Second),

5PPS, 10PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz

associated with a selectable reference clock input

• Per-input programmable phase offset of up to ±1.638s in 1ps steps

▪ Three GPIOs can be configured as single-ended clock inputs

supporting frequencies from 0.5Hz to 150MHz

▪ Reference monitors qualify/disqualify references depending on

LOS, activity, frequency monitoring, and/or LOS input pins

• Loss of Signal (LOS) input pins (via GPIOs) can be assigned

to any input clock reference