▪ Ultra-low phase noise synthesizer with jitter below

25fs RMS, 12kHz to 20MHz with 4MHz HPF

▪ Two independent low phase noise sync domains

▪ Four independent low phase noise frequency domains

▪ Support for JESD204B/C

▪ Time sync block with time to digital converter

(TDC), time of day (TOD) counter, and PTP clocks

▪ 8 clock outputs with independent integer dividers

• 6: LVDS, HCSL (AC-LVPECL) or CML

• 2: LVDS, HCSL (AC-LVPECL) or LVCMOS

▪ Output frequency range:

• CML: DC to 2.5GHz

• LVDS or HCSL: DC to 1GHz

• LVCMOS: DC to 250MHz

▪ Two differential clock inputs configurable as four

single-ended clock inputs

▪ Operates from a 1.8V supply.

▪ Clock inputs tolerate 1.8V input when the device is

powered off, sinking less than 1mA

▪ CLKIN input frequency range: DC to 1GHz

▪ Time Sync TDC supports 1PPS and PP2S inputs

▪ DPLLs comply with ITU-T G.8262 and G.8262.1

▪ DPLL input-to-output phase variation ≤ 100ps

▪ DCO frequency resolution < 10-13

▪ Package: 7 × 7 mm, 64-BGA