▪ 32-bit CPU + FPU, MMU option

▪ CPU with integrated vector FPU

− 7MFLOPS / MHz

▪ Dual issue 32-bit CPU

− 1.5DMIPS / MHz

▪ 5-stage pipeline

▪ Configurable

− 2-way 4, 8, 16, 32, 64k I and D cache sizes

− Optional emulation, peripheral facility

▪ Synthesizable core

▪ Peripherals

− CSP(Core Support Peripherals)

− ESP(Emulation Support Peripherals)