位置:PCM4L > PCM4L详情

PCM4L中文资料

厂家型号

PCM4L

文件大小

2196.7Kbytes

页面数量

38

功能描述

PTP Clock Manager for Linux

数据手册

下载地址一下载地址二到原厂下载

生产厂商

Renesas Technology Corp

简称

RENESAS瑞萨

中文名称

瑞萨科技有限公司官网

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PCM4L数据手册规格书PDF详情

The PTP Clock Manager for Linux (pcm4l) is designed as a high-performance clock recovery solution for packet-based time/phase/frequency synchronization. The pcm4l software includes the

features required to meet the ITU-T Telecom packet equipment clock recommendations, including a

packet clock state machine. In complex networks with partially unknown packet delays, typical in telecom applications, pcm4l offers patented filter algorithms that help to improve synchronization accuracy with time/phase accuracy of under 1 microsecond and frequency accuracy of under 16 parts-per-billion (ppb). In networks with full IEEE 1588 support that are made up of Boundary Clock (BC) or Transparent Clock (TC) nodes, the pcm4l offers an outlier detection algorithm,

used in conjunction with the Renesas ITU-T G.8273.2 hardware filter, which helps to improve

synchronization accuracy with time/phase accuracy of under 5ns filtered (provisional Class D). These tight requirements dictate the use of timing hardware for the synthesis of the physical clock.

The adaptive servo is implemented in software running on a host processor that controls the PTP

Hardware Clock (PHC). The IEEE 1588 protocol also runs on a host processor but does not need to be colocated with pcm4l (i.e., a different processor). The pcm4l architecture and interfaces makes it ideal for open-source architectures, such as White Box hardware and O-RAN. For more information about the PTP Clock Manager, see the pcm4l product page.

Features

▪ Filters the effects of high Packet Delay Variation

(PDV) per G.8273.4 or G.8263

▪ Calibrates for asymmetry when an external local

time reference is available per G.8273.4 APTS

▪ Software provided as clear C code, ready for Linux

distributions

• Runs on Linux kernel v3.0 and higher, using the

PTP Hardware Clock Infrastructure for clock

control

• Dramatically simplifies software integration and

debugging

▪ Support for IEEE1588-2019 Slave Event

Monitoring channel to allow for a timestamp

interface to an external PTP stack

▪ Full PTP clock state machine per ITU-T G.8275.1

Appendix V and G.8275.2 Appendix IV

Applications

▪ Wireless infrastructure for 4.5G and 5G network

equipment

▪ Phase/time synchronization with full timing support

from the network per ITU-T G.8275.1

• Telecom Boundary Clocks (T-BCs) and Telecom

Time Slave Clocks (T-TSCs) according to ITU-T

G.8273.2 for Full Timing Support (FTS) networks

▪ Phase/time synchronization with assisted or partial

timing support from the network per ITU-T

G.8275.2

• Telecom Boundary Clocks (T-BCs) and Telecom

Time Slave Clocks (T-TSCs) according to ITU-T

G.8273.4 for Assisted Partial Timing Support

(APTS) or Partial Timing Support (PTS)

networks

更新时间:2025-5-15 11:02:00
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Renesas Technology Corp 瑞萨科技有限公司

中文资料: 113790条

瑞萨科技公司(Renesas Technology Corp.)是一家全球领先的半导体解决方案供应商,总部位于日本东京。公司成立于2002年,由原日立半导体和三菱电机半导体合并而成,专注于提供高性能和高效能的微控制器、模拟和混合信号IC、功率半导体以及系统集成解决方案,广泛应用于汽车、工业控制、信息通信、消费电子等多个领域。瑞萨科技的产品组合涵盖微控制器(MCUs)、模拟和混合信号IC、功率半导体以及汽车解决方案等。公司在汽车电子领域具有强大的技术实力,提供车载MCU、传感器和网络解决方案,支持智能汽车的发展。瑞萨在全球设有多个研发中心和分支机构,产品及解决方案销售至欧美、亚洲等地区,致力于为