• Single supply 1.8V operation

• Clock duty cycle stabilizer

• 75fs clock jitter

• 700MHz bandwidth

• Programmable built-in test patterns

• Multi-ADC support

- SPI programmable fine gain and offset control

- Support for multiple ADC synchronization

- Optimized output timing

• Nap and sleep modes

- 200μs sleep wake-up time

• Data output clock

• SDR/DDR LVDS-compatible or LVCMOS outputs

• Selectable clock divider