• Single Supply 1.8V Operation

• Clock Duty Cycle Stabilizer

• 75fs Clock Jitter

• 700MHz Bandwidth

• Programmable Built-in Test Patterns

• Multi-ADC Support

- SPI Programmable Fine Gain and Offset Control

- Support for Multiple ADC Synchronization

- Optimized Output Timing

• Nap and Sleep Modes

- 200μs Sleep Wake-up Time

• Data Output Clock

• SDR/DDR LVDS-Compatible or LVCMOS Outputs

• Selectable Clock Divider