Features

• Ten low skew, low additive jitter LVPECL outputs

• Two selectable, differential LVPECL clock inputs

• Differential pairs can accept the following differential input

levels: LVDS, LVPECL and CML

• Maximum input clock frequency: 2.5GHz

• LVCMOS interface levels for the control input (input select)

• Output skew: 15ps (typical)

• Propagation delay: 250ps (typical)

• Additive phase jitter, RMS; fREF = 156.25MHz (12kHz - 20MHz):

30fs (typical)

• Full 3.3V and 2.5V supply voltage

• Maximum device current consumption (IEE): 126mA

• Lead-free (RoHS 6) 32-Lead VFQFN package

• -40°C to 85°C ambient operating temperature