FEATURES:

• 1.8V Operation

• SSTL_18 style clock and data inputs

• Differential CLK input

• Configurable as 25-bit 1:1 or 14-bit 1:2 registered buffer

• Control inputs compatible with LVCMOS levels

• Flow-through architecture for optimum PCB design

• Latch-up performance exceeds 100mA

• ESD >2000V per MIL-STD-883, Method 3015; >200V using

machine model (C = 200pF, R = 0)

• Checks parity on data inputs

• Available in 96-pin LFBGA package