Features/Benefits

• Low additive jitter; suitable for use in PCIe Gen2 and

Gen3 systems

• 16-pin TSSOP package; small board footprint

• Outputs can be terminated to LVDS; can drive a wider

variety of devices

• OE control pin; greater system power management

• Industrial temperature range available; supports

demanding embedded applications

Key Specifications

• Additive cycle-to-cycle jitter <5 ps

• Additive phase jitter (PCIe Gen3) <0.2ps

• Operating frequency up to 200MHz