FEATURES:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five and one bank of

four outputs

• Separate output enable for each output bank

• Output Skew < 250ps

• Low jitter <175 ps cycle-to-cycle

• 50ps typical cycle-to-cycle jitter (15pF, 66MHz)

• IDT2309B-1 for Standard Drive

• IDT2309B-1H for High Drive

• No external RC network required

• Operates at 3.3V VDD

• Available in SOIC and TSSOP packages