• Five differential HSTL compatible outputs

• Selectable differential CLK0, CLK0 or LVCMOS/LVTTL clock

inputs

• CLK0, CLK0 pair can accept the following differential input

levels: LVPECL, LVDS, HSTL, HCSL, SSTL

• CLK1 can accept the following input levels: LVCMOS or LVTTL

• Output frequency up to: 700MHz

• Translates any single-ended input signal to HSTL levels with

resistor bias on CLK0 input

• Output skew: 30ps (maximum)

• Part-to-part skew: 250ps (maximum)

• Propagation delay: 1.8ns (maximum)

• 3.3V core, 1.8V output operating supply

• 0°C to 85°C ambient operating temperature

• Industrial temperature information available upon request

• Available in lead-free (RoHS 6) package

• For functional replacement part use 8523