FEATURES

• Three banks of outputs: one bank of two LVDS outputs

and two banks of one LVPECL output

• Selectable crystal oscillator interface or

LVCMOS/LVTTL single-ended reference clock input

• Four independently selectable output frequency on each

bank: 318.75MHz, 212.5MHz, 159.375MHz and 106.25MHz

• Maximum output frequency: 318.75MHz

• Crystal input frequency: 25.5MHz

• VDDO_LVPECL can be set for 3.3V or 2.5V, allowing the

device to generate 3.3V or 2.5V LVPECL levels

• RMS phase jitter at 106.25MHz, using a 25.5MHz crystal

(637kHz to 10MHz intergration): 2.65ps (typical)