Features

• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bits

• Conversion Rate 125 MSPS (PECL)

100 MSPS (TTL)

• Data Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TTL

• Low Power Consumption . . . . . . . . . . . . . . . 400mW (Typ)

• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . 1.5pV•s

• Clock, Reset Input Level: TTL and PECL Compatible 2:1

Multiplexed Input Function

• 1/2 Frequency-Divided Clock Output Possible by the Built-

In Clock Frequency Divider Circuit

• Voltage Output (50Ω Load Drive Possible)

• Single Power Supply or ±Dual Power Supplies

• Polarity Switching Function of Reset Signal

Applications

• LCD

• DDS

• HDTV

• Communications (QPSK, QAM)