▪ Small gate size

▪ Common interface with H8S CPU subsystem IP

− system (reset and clock) interface

− bus interface

− interrupt interface

▪ Sharable peripheral modules (option) with H8S CPU subsystem

− 16-bit free-running timer (FRT)

− 8-bit timer

− 14-bit PWM timer

− 8-bit PWM timer

− Watchdog timer (WDT)

− Serial communication interface

▪ RTL design using Verilog

▪ Applicable to various processes and FPGAs