10-bit resolution

Sampling rate up to 50 MHz

DC sampling allowed

One clock cycle conversion only

High signal-to-noise ratio over a large analog input frequency range (9.4 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz)

No missing codes guaranteed

In-Range (IR) CMOS output

TTL and CMOS levels compatible digital inputs

3 V to 5 V CMOS digital outputs

Low-level AC clock input signal allowed

External reference voltage regulator

Power dissipation only 175 mW (typical)

Low analog input capacitance, no buffer amplifier required

No sample-and-hold circuit required