Features/Benefits

• Space-saving 64-pin packages

• Fixed feedback path/ 0ps input-to-output delay

• 9 Selectable SMBus Addresses/Mulitple devices can share

the same SMBus Segment

• 12 OE# pins/Hardware control of each output

• PLL or bypass mode/PLL can dejitter incoming clock

• 100MHz or 133MHz PLL mode operation/supports PCIe

and QPI applications

• Selectable PLL bandwidth/minimizes jitter peaking in

downstream PLL's

• Spread Spectrum Compatible/tracks spreading input clock

for low EMI

• Software control of PLL Bandwidth and Bypass Settings/

PLL can dejitter incoming clock (B Rev only)

Output Features

• 12 - 0.7V differential HCSL output pairs