• 1.8V operation; reduced power consumption

• OE# pins; support DIF power management

• LP-HCSL differential clock outputs; reduced power and

board space

• Programmable Slew rate for each output; allows tuning

for various line lengths

• Programmable output amplitude; allows tuning for

various application environments

• DIF outputs blocked until PLL is locked; clean system

start-up

• Selectable 0%, -0.25% or -0.5% spread on DIF outputs;

reduces EMI

• External 25MHz crystal; supports tight ppm with 0 ppm

synthesis error

• Configuration can be accomplished with strapping pins;

SMBus interface not required for device control

• 3.3V tolerant SMBus interface works with legacy

controllers

• Space saving 5 x 5 mm 32-QFN; minimal board space

• Selectable SMBus addresses; multiple devices can

easily share an SMBus segment