Features/Benefits

• LP-HCSL outputs; save 16 resistors compared to standard

PCIe devices

• 50mW typical power consumption; reduced thermal

concerns

• Outputs can optionally be supplied from any voltage

between 1.05 and 1.5V; maximum power savings

• OE# pins; support DIF power management

• Programmable Slew rate for each output; allows tuning for

various line length

• Programmable output amplitude; allows tuning for various

application environments

• DIF outputs blocked until PLL is locked; clean system

start-up

• Selectable 0, -0.25 or -0.5 spread on DIF outputs;

reduces EM

• External 25MHz crystal; supports tight ppm with 0 ppm

synthesis error

• Configuration can be accomplished with strapping pins;

SMBus interface not required for device control

• Selectable SMBus addresses; multiple devices can easily

share an SMBus segment

• 3.3V tolerant SMBus interface works with legacy controllers

• Space saving 48-pin 6x6 mm VFQFPN; minimal board

space