▪ Automatically detects presence or absence of input clocks

▪ Integrated terminations on LP-HCSL outputs save 8 resistors

▪ 201, 301 configurations for SRnS (IR) or CC architectures

default to 0% SSC

▪ 202, 302 configurations for SRIS (IR) or CC architectures

default to -0.5% SSC

• SMBus-selectable -0.25% SSC

▪ Choice of 25MHz or 33 1/3MHz reference clock

▪ REF clock output; saves external XO

▪ 2.5V to 3.3V operating voltage (VDDREF is 1.8V)

▪ 4 × 4 mm 28-VQFP-N package with external crystal

▪ 4 × 4 mm 28-LGA package with optional internal crystal

▪ Contact factory for other configurations