▪ Four differential inputs support LVPECL, LVDS, HCSL or

LVCMOS reference clocks

▪ Flexible Power Sequencing (FPS) ensures good behavior

when powered up without input clock, or when the input clock

is present without power

▪ Power-Down Tolerant (PDT) inputs: CLK_SEL_tri, OE pins,

IOA_tri, IOB_tri, ZOUTSEL may be driven when the 9DML4493

is not powered up

▪ Accepts input frequencies ranging from 1PPS (1Hz) to 350MHz

▪ Configured via pin straps - no serial bus needed

• Pin-selectable 100Ω or 85Ω differential output impedance

• Three pin-selectable output amplitudes per bank

• Pin-selectable 4:4 mode or dual 2:2 MUX modes

▪ Glitch-free output enable pins for each output

▪ Spread-spectrum tolerant

▪ Voltage supply of 1.8V, 2.5V, or 3.3V

▪ -40°C to +85°C ambient operating temperature

▪ 5 × 5 mm 32-VFQFPN package