• Direct connection to 100 transmission lines; saves 8

resistors compared to standard HCSL outputs

• 35mW typical power consumption in PLL mode;

eliminates thermal concerns

• Spread Spectrum (SS) compatible; allows SS for EMI reduction

• OE# pins; support DIF power management

• HCSL-compatible differential input; can be driven by

common clock sources

• SMBus-selectable features; optimize signal integrity to application:

• Slew rate for each output

• Differential output amplitude

• Pin/SMBus selectable PLL bandwidth and PLL Bypass;

optimize PLL to application

• Outputs blocked until PLL is locked; clean system start-up

• Device contains default configuration; SMBus interface

not required for device control

• 3.3V tolerant SMBus interface works with legacy controllers

• Space saving 24-pin 4 x 4 mm VFQFPN; minimal board space