Recommended Application:

Single-ended clock input with zero delay board fan out

Product Description/Features:

• Low skew, low jitter PLL clock driver

• 1 to 10 differential clock distribution (SSTL_2)

• Feedback pin for input to output synchronization

• PD# for power management

• Spread Spectrum tolerant inputs

Switching Characteristics:

• CYCLE - CYCLE jitter: <60ps

• OUTPUT - OUTPUT skew: <60ps

• Period jitter: ±30ps

• DUTY CYCLE: 49.5 - 50.5