Features/Benefits

• Spread Spectrum; EMI reduction

• Outputs may be disabled via SMBus; saves power

• External crystal load capacitors; maximum frequency

accuracy

Key Specifications

• CPU output cycle-to-cycle jitter <100ps

• SRC output cycle-to-cycle jitter <125ps

• 48MHz output cycle-to-cycle jitter <130ps

• SIO output cycle-to-cycle jitter <150ps

• SRC output phase jitter <3.1ps rms (PCIe Gen2)

• +/- 50ppm frequency accuracy on all clocks, assuming

REF is trimmed to 0 ppm)