General Description

The 8V34S204 is a differential 1:4 LVDS fanout buffer with a 2:1 input

multiplexer. The device accepts DC to 250MHz clock and data

signals and is designed for 1Hz clock /1PPS, 2kHz and 8kHz signal

distribution. Controlled by the input mode selection pin, the

differential input stages accept both rectangular or sinusoidal signals.

The 8V34S204 also provides level translated LVCMOS/LVTTL

outputs which are copies of the individual differential inputs CLKA

and CLKB. The propagation delay of the device is very low, providing

an ideal solution for clock distribution circuits with tight phase

alignment requirements. The multiplexer select pin (SEL) allows to

select one out of two input signals, which is copied to the four

differential outputs.

Features

• Designed for 1PPS, 2kHz, 8kHz and 10MHz GPS clock signal

distribution

• High speed 1:4 LVDS fanout buffer

• Four differential LVDS output pairs

• 2:1 input multiplexer

• Two selectable differential inputs accept LVDS and LVPECL signals

• Accepts rectangular and sinusoidal input signals

• Two input monitoring outputs (LVCMOS)

• Max Output frequency: 250MHz

• Additive phase jitter, RMS;

12kHz to 20MHz: = 65fs at 156.25MHz (typical)

• Part-to-part skew: 200ps (maximum)

• Propagation delay (differential outputs): 350ps (typical)

• Full 2.5V and 3.3V voltage supply

• -40°C to 85°C ambient operating temperature

• Lead-free 24-lead VFQFN (RoHS 6/6) packaging