Features

• Two differential reference clock input pairs

• Differential input pairs can accept the following differential input

levels: LVPECL, LVDS, HCSL

• Crystal Oscillator Interface

• Crystal input frequency range: 10MHz to 40MHz

• Maximum Output Frequency

LVPECL - 2GHz

LVDS - 2GHz

HCSL - 250MHz

LVCMOS - 250MHz

• Two banks, each has five differential output pairs that can be

configured as LVPECL or LVDS or HCSL

• One single-ended reference output with synchronous enable to

avoid clock glitch

• Output skew: (Bank A and Bank B at the same output level)

70ps (max)

• Part-to-part skew: 250ps (max)

• Additive RMS phase jitter: 0.153ps (typical)

• Supply voltage modes:

VDD/VDDO

3.3V/3.3V

3.3V/2.5V

2.5V/2.5V

• -40°C to 85°C ambient operating temperature

• Lead-free (RoHS 6) packaging