• Two differential reference clock input pairs

• Differential input pairs can accept the following input

levels: LVPECL, LVDS, HCSL, HSTL and Single-ended

• Crystal Oscillator Interface

• Crystal input frequency range: 10MHz to 40MHz

• Maximum Output Frequency:

LVPECL – 2GHz

LVDS – 2GHz

HCSL – 250MHz

LVCMOS – 250MHz

• Two banks, each has three differential output pairs that can be

configured as LVPECL or LVDS or HCSL

• One single-ended reference output with synchronous enable to

avoid clock glitch

• Output skew: 80ps (maximum)

(Bank A and Bank B at the same output level)

• Part-to-part skew: 200ps (typical)

• Additive RMS phase jitter at 156.25MHz, (12kHz–20MHz):

34.7fs (typical), 3.3V/ 3.3V

• Supply voltage modes:

VDD/VDDO

3.3V/3.3V

3.3V/2.5V

2.5V/2.5V

• -40°C to +85°C ambient operating temperature

• Lead-free (RoHS 6) packaging