Description

The 8T39210 is a high-performance clock fanout buffer. The input

clock can be selected from two differential inputs or one crystal

input. The internal oscillator circuit is automatically disabled if the

crystal input is not selected. The crystal pin can be driven by a

single-ended clock. The selected signal is distributed to ten

differential outputs that can be configured as LVPECL, LVDS, or

HCSL outputs. In addition, an LVCMOS output is provided. All

outputs can be disabled into a high-impedance state.

The device is designed for a signal fanout of high-frequency, low

phase-noise clock and data signal. The outputs are at a defined

level when inputs are open or tied to ground. It is designed to

operate from a 3.3V or 2.5V core power supply, and either a 3.3V

or 2.5V output operating supply.

Features

▪ Two differential reference clock input pairs

▪ Differential input pairs can accept the following differential

input levels: LVPECL, LVDS, HCSL, HSTL, or Single ended

▪ Crystal Input accepts 10MHz to 40MHz Crystal or

Single-ended Clock

▪ Maximum Output Frequency

• LVPECL - 1.5GHz

• LVDS - 1.5GHz

• HCSL - 750MHz

• LVCMOS - 250MHz

▪ Two banks, each has five differential output pairs that can be

configured as LVPECL, LVDS, or HCSL

▪ One single-ended reference output with synchronous enable to

avoid clock glitch

▪ Output skew: 81ps (maximum)

(Bank A and Bank B at the same output level)

▪ Part-to-part skew: 200ps (typical)

▪ Additive RMS phase jitter at 156.25MHz:

37.6fs RMS (12kHz - 20MHz), typical at 3.3V/3.3V

▪ Supply voltage modes:

• VDD/VDDO

• 3.3V/3.3V

• 3.3V/2.5V

• 2.5V/2.5V

▪ -40°C to 85°C ambient operating temperature

▪ Lead-free (RoHS 6) packaging