Features

• Two low skew, low additive jitter LVPECL output pairs

• Two selectable, differential clock input pairs

• Differential pairs can accept the following differential input

levels: LVDS, LVPECL, CML

• Maximum input clock frequency: 2GHz

• Output skew: 5ps (typical)

• Propagation delay: 225ps (maximum)

• Low additive phase jitter, RMS, fREF = 156.25MHz, VPP = 1V,

12kHz – 20MHz: 36fs (maximum)

• Full 3.3V and 2.5V supply voltage

• Maximum device current consumption (IEE): 56mA (maximum)

• Available in lead-free (RoHS 6), 16-Lead VFQFPN package

• -40°C to 85°C ambient operating temperature

• Supports case temperature ≤105°C operations

• Accepts single-ended LVCMOS levels. See Applications section

• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also

accept single-ended LVCMOS levels. See Applications section

Wiring the Differential Input Levels to Accept Single-ended Levels

(Figure 1A and Figure 1B)