• Eight low skew, low additive jitter LVDS output pairs

• Two selectable, differential clock input pairs

• Differential PCLK, nPCLK pairs can accept the following

differential input levels: LVDS, LVPECL

• Maximum input clock frequency: 2GHz (maximum)

• LVCMOS/LVTTL interface levels for the control select input

• Output skew: 8ps (typical)

• Propagation delay: 240ps (typical)

• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,

10kHz - 20MHz: 82fs (typical)

• Maximum device current consumption (IDD):

190mA (maximum) at 3.465V

• 3.3V supply voltage

• Lead-free (RoHS 6), 28-Lead VFQFN package

• -40°C to 85°C ambient operating temperature