▪ Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS

reference clocks

— Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz

▪ Select which of the two input clocks is to be used as the reference

clock for which divider via pin or register selection

— Switchover will not generate any runt clock pulses on the output

▪ Generates eight differential outputs

or eight LVCMOS outputs, Bank A only

— Differential outputs selectable as LVPECL, LVDS, CML or HCSL

— Differential outputs support frequencies from 1PPS to 700MHz

— LVCMOS outputs support frequencies from 1PPS to 200MHz

— LVCMOS outputs in the same pair may be inverted or in-phase

relative to one another

▪ Outputs arranged in 2 banks of 4 outputs each

— Each bank supports a separate power supply of 3.3V, 2.5V or 1.8V

— 1.5V output voltage is also supported for LVCMOS, Bank A only

— One divider per output bank, supporting divide ratios of 2...511 or divider bypass

▪ Output enable control pin

— Output enable or disable will not cause any runt pulses

▪ Register programmable via I2C / SPI serial port

— Individual output enables, output type selection and output

power-down control bits supported

— Input mux selection control bit

▪ Core voltage supply of 3.3V, 2.5V or 1.8V

▪ -40°C to +85°C ambient operating temperature

▪ Lead-free (RoHS 6) packaging