• Eight low skew, low additive jitter LVDS output pairs

• Two selectable, differential clock input pairs

• Differential CLK, nCLK pairs can accept the following

differential input levels: LVDS, CML

• Maximum input clock frequency: 1.5GHz

• LVCMOS/LVTTL interface levels for the control input select pin

• Output skew: 20ps (typical)

• Propagation delay: 400ps (maximum)

• Low propagation delay variation across temperature for 1PPS

applications

• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,

12kHz–20MHz: 34fs (typical)

• Device current consumption (IDD):

• 120mA typical: 1.8V

• 132mA typical: 2.5V

• Full 1.8V or 2.5V supply voltage

• Lead-free (RoHS 6), 28-Lead VFQFPN packaging

• -40°C to +85°C ambient operating temperature

• Supports case temperature up to +105°C

• Supports PCI Express Gen1–5