Features

• Six low skew, low additive jitter LVDS output pairs

• One differential clock input pair

• Differential CLK, nCLK pair can accept the following differential

input levels: LVDS, CML

• Maximum input clock frequency: 1.2GHz (maximum)

• Output skew: 20ps (typical)

• Propagation delay: 290ps (typical)

• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,

12kHz–20MHz: 39fs (typical)

• Full 1.8V supply voltage

• Lead-free (RoHS 6), 20-Lead VFQFN packaging

• -40°C to 85°C ambient operating temperature