Features

• Two LVDS and two 0.7V differential output pairs

Bank A has two LVDS output pairs and

Bank B has two 0.7V differential output pairs

• One differential clock input pair

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Output frequency range: 98MHz - 160MHz

• Input frequency range: 98MHz - 128MHz

• VCO range: 490MHz - 640MHz

• Cycle-to-cycle jitter: 35ps (maximum)

• Full 3.3V operating supply

• Three bandwidth modes allow the system designer to make jitter

attenuation/tracking skew design trade-offs

• -40°C to 85°C ambient operating temperature

• Available in lead-free packages