FEATURES

• 5 differential 2.5V/3.3V LVPECL outputs

• Selectable differential CLK0, nCLK0 or LVCMOS inputs

• CLK0, nCLK0 pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• CLK1 can accept the following input levels:

LVCMOS or LVTTL

• Maximum output frequency: 700MHz

• Translates any single-ended input signal to 3.3V

LVPECL levels with resistor bias on nCLK input

• Output skew: 30ps (maximum), TSSOP package

50ps (maximum), SOIC package

• Part-to-part skew: 350ps (maximum)

• Propagation delay: 1.8ns (maximum)

• RMS phase jitter @ 155.52MHz (12kHz - 20MHz):

0.05ps (typical)

• LVPECL mode operating voltage supply range:

VCC = 2.375V to 3.8V, VEE = 0V

• -40°C to 85°C ambient operating temperature

• Available in lead-free RoHS-compliant package