FEATURES

• 4 differential LVHSTL compatible outputs

• Selectable differential CLK0, nCLK0 and CLK1, nCLK1

clock inputs

• Clock input pairs can accept the following differential

input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

• Maximum output frequency: 650MHz

• Translates any single-ended input signal to LVHSTL

levels with resistor bias on nCLK input

• Output skew: 50ps (maximum)

• Part-to-part skew: 400ps (maximum)

• Propagation delay: 1.2ns (typical)

• VOH = 1V (maximum)

• 3.3V core, 1.8V output operating supply

• Lead-Free package available

• -40°C to 85°C ambient operating temperature