FEATURES

• Five 0.7V differential HCSL outputs

• Selectable differential CLK0, nCLK0 or LVCMOS inputs

• CLK0, nCLK0 pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL

• CLK1 can accept the following input levels:

LVCMOS or LVTTL

• Maximum output frequency: 500MHz

• Translates any single-ended input signal to 3.3V

HCSL levels with resistor bias on nCLK input

• Output skew: 100ps (maximum)

• Part-to-part skew: 600ps (maximum)

• Propagation delay: 3.2ns (maximuml)

• Additive phase jitter, RMS: 0.24ps (typical)

• 3.3V operating supply

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package