Features

• One LVCMOS/LVTTL output

• Differential CLK/nCLK input pair

• CLK/nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Output frequency: 350MHz (typical)

• Part-to-part skew: 500ps (maximum)

• Additive phase jitter, RMS: 0.21ps (typical), 3.3V output

• Full 3.3V and 2.5V operating supply

• -40°C to 85°C ambient operating temperature