FEATURES:

• 64 x 36 storage capacity

• Supports clock frequencies up to 67MHz

• Fast access times of 10ns

• Free-running CLKA and CLKB may be asynchronous or

coincident (permits simultaneous reading and writing of

data on a single clock edge)

• Synchronous data buffering from Port A to Port B

• Mailbox bypass register in each direction

• Programmable Almost-Full (AF) and Almost-Empty (AE) flags

• Microprocessor Interface Control Logic

• Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA

• Empty Flag (EF) and Almost-Empty (AE) flags synchronized by

CLKB

• Passive parity checking on each Port

• Parity Generation can be selected for each Port

• Available in space-saving 120-pin Thin Quad Flatpack (PFG)

• Green parts available, see ordering information