Features

◆ True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

◆ High-speed access

– Commercial: 25/35/55ns (max.)

◆ Low-power operation

– IDT70V26S

Active: 300mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V26L

Active: 300mW (typ.)

Standby: 660μW (typ.)

◆ Separate upper-byte and lower-byte control for multiplexed

bus compatibility

◆ IDT70V26 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

◆ M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

◆ On-chip port arbitration logic

◆ Full on-chip hardware support of semaphore signaling

between ports

◆ Fully asynchronous operation from either port

◆ TTL-compatible, single 3.3V (±0.3V) power supply

◆ Available in 84-pin PGA and PLCC

◆ Green parts available, see ordering information