Features

• Fully integrated PLL, no external loop filter required

• Differential 3.3 V LVPECL outputs

• Uses fundamental crystal or clock

— Crystal input frequency: 10 to 27MHz

— Clock input: 10 to 38MHz (mulitply by 6)

10 to 31MHz (all other multiply settings)

• Output clocks up to 230 MHz at 3.3 V

• Low phase noise: -122 dBc/Hz at 10 kHz

• Low jitter - 15 ps one sigma typ.

• Powerdown mode lowers power consumption

• Packaged in 16-pin TSSOP, Pb-free

• Advanced, low power, sub-micron CMOS process

• Operating voltage of 3.3 V

• Commercial temperature range available