FEATURES:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five outputs

• Zero Input-Output Delay

• Output Skew < 250ps

• Low jitter <175 ps cycle-to-cycle

• 50ps typical cycle-to-cycle jitter (15pF, 66MHz)

• IDT2305B-1 for Standard Drive

• IDT2305B-1H for High Drive

• No external RC network required

• Operates at 3.3V VDD

• Power down mode

• Available in SOIC and TSSOP packages