DESCRIPTION

MB85RS2MLY is a FeRAM (Ferroelectric Random Access Memory) chip in a configuration of 262,144

words  8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming

the nonvolatile memory cells. This product is specifically targeted for high-temperature environment such

as automotive applications.

MB85RS2MLY adopts the Serial Peripheral Interface (SPI).

The MB85RS2MLY is able to retain data without using a back-up battery, as is needed for SRAM.

The memory cells used in the MB85RS2MLY can be used for 1013 read/write operations, which is a significant

improvement over the number of read and write operations supported by Flash memory and E2PROM.

As MB85RS2MLY does not need any waiting time in writing process, the write cycle time of MB85RS2MLY

is much shorter than that of Flash memories or E2PROM.

FEATURES

• Bit configuration : 262,144 words  8 bits

• Special Sector Region : 256 words  8 bits

In this region, data storage after (by) three times reflow based on

JEDEC MSL-3 standard condition is guaranteed.

• Unique ID

• Serial Number : 64 bits

In this region, data storage after (by) three times reflow based on

JEDEC MSL-3 standard condition is guaranteed.

• Serial Peripheral Interface : SPI (Serial Peripheral Interfaces)

Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)

• Operating frequency : 50 MHz (Max)

• High endurance : 1013 times / byte

• Data retention : 50.4 years (+85 C)

13.7years (+105 C)

4.2 years (+125 C) or more

Under evaluation for more than 4.2years(+125 C)

• Operating power supply voltage : 1.7 V to 1.95 V

• Low power consumption : Operating power supply current 3.5 mA (Max@50 MHz)

Standby current 200 A (Max)

• Operation ambient temperature range :  40 C to +125 C

• Package : 8-pin plastic SOP 150mil

8-pin plastic DFN 5mm  6mm

AEC-Q100 Grade 1 compliant

RoHS compliant