Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator

General Description The RT9173D is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requ

3A DDR 总线终端电压调节器

RT9173D 是简单好用、性价比高的高速线性调节器，被设计用于为符合 JEDEC SSTL_2 和 SSTL_18 规范的 DDR 内存系统或具有 HSTL 、 SCSI-2 和 SCSI-3 等接口的设备生成终端匹配电压。该调节器具有在 40mV 电压误差范围内动态吸入或是释出 2A （瞬态峰值 3A ）电流的能力，其输出电压能够精确地跟踪由两只外部电阻分压器所形成的 1/2V_DDQ 电压或是其它希望的电压，该电压经由 REFEN 引脚输入至调节系统中。RT9173D 内部包含了一个高速查分运算放大器，这成为它对线路/负载瞬态过程的超快速响应的支撑。它的其它特性包括了 • DDR, DDR-II 和 DDR-III VTT 应用的理想选择\n• 2A 连续电流\n• 峰值 2.5A 电流支持 DR-III\n• 为 SSTL_2, SSTL_18, HSTL, SCSI-2 和 SCSI-3 接口生成终端匹配电压\n• 输出由两只外部电阻调整\n• 关机时对 RAM 的挂起状态呈现为高阻输出\n• 内置热保护\n• VIN 和 VCNTL 之间无电源时序问题\n• 符合 RoHS 规范，完全无铅;

Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator

文件：223.87 Kbytes Page：13 Pages

Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator

General Description The RT9173D is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requ

Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator

General Description The RT9173D is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requ

Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator

文件：223.87 Kbytes Page：13 Pages

Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator

文件：223.87 Kbytes Page：13 Pages

封装/外壳：8-SOIC（0.154"，3.90mm 宽）裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC REG CONV DDR BUS 1OUT 8SOP 集成电路（IC） 特殊用途稳压器

Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator

文件：223.87 Kbytes Page：13 Pages

Digital Subscriber Interface Circuit with RxSB

Description The MT9173 (DSIC) and MT9174 (DNIC) are functionally identical to the MT9171/72 except for the addition of one feature. The MT9173/74 include a digital output pin indicating the temporal position of the received SYNC bit of the biphase transmission. This feature is especially useful

Digital Subscriber Interface Circuit with RxSB

Description The MT9173 (DSIC) and MT9174 (DNIC) are functionally identical to the MT9171/72 except for the addition of one feature. The MT9173/74 include a digital output pin indicating the temporal position of the received SYNC bit of the biphase transmission. This feature is especially useful

Digital Subscriber Interface Circuit with RxSB

Description The MT9173 (DSIC) and MT9174 (DNIC) are functionally identical to the MT9171/72 except for the addition of one feature. The MT9173/74 include a digital output pin indicating the temporal position of the received SYNC bit of the biphase transmission. This feature is especially useful

Digital Subscriber Interface Circuit with RxSB

Description The MT9173 (DSIC) and MT9174 (DNIC) are functionally identical to the MT9171/72 except for the addition of one feature. The MT9173/74 include a digital output pin indicating the temporal position of the received SYNC bit of the biphase transmission. This feature is especially useful

Quad LVDS Line Receiver with Flow-Through Pinout and ?쏧n-Path??Fail-Safe

文件：277.96 Kbytes Page：14 Pages