True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz

1.1 Features Ultra-low power consumption technology  VDD = single power supply voltage of 1.6 to 5.5 V  HALT mode  STOP mode  SNOOZE mode RL78 CPU core  CISC architecture with 3-stage pipeline  Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz

True Low Power Platform

文件：1.74099 Mbytes Page：202 Pages

PG-FP5

文件：153.47 Kbytes Page：17 Pages

True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz

1.1 Features Ultra-low power consumption technology  VDD = single power supply voltage of 1.6 to 5.5 V  HALT mode  STOP mode  SNOOZE mode RL78 CPU core  CISC architecture with 3-stage pipeline  Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz

True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz

1.1 Features Ultra-low power consumption technology  VDD = single power supply voltage of 1.6 to 5.5 V  HALT mode  STOP mode  SNOOZE mode RL78 CPU core  CISC architecture with 3-stage pipeline  Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz

True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz

1.1 Features Ultra-low power consumption technology  VDD = single power supply voltage of 1.6 to 5.5 V  HALT mode  STOP mode  SNOOZE mode RL78 CPU core  CISC architecture with 3-stage pipeline  Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz

True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz

1.1 Features Ultra-low power consumption technology  VDD = single power supply voltage of 1.6 to 5.5 V  HALT mode  STOP mode  SNOOZE mode RL78 CPU core  CISC architecture with 3-stage pipeline  Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz

True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz

1.1 Features Ultra-low power consumption technology  VDD = single power supply voltage of 1.6 to 5.5 V  HALT mode  STOP mode  SNOOZE mode RL78 CPU core  CISC architecture with 3-stage pipeline  Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz

True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz

1.1 Features Ultra-low power consumption technology  VDD = single power supply voltage of 1.6 to 5.5 V  HALT mode  STOP mode  SNOOZE mode RL78 CPU core  CISC architecture with 3-stage pipeline  Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz

True Low Power Platform

文件：1.74099 Mbytes Page：202 Pages

PG-FP5

文件：153.47 Kbytes Page：17 Pages