FEATURES

• Single-chip multi-channel packet processor supporting a maximum aggregate bandwidth of 156 Mbit/s for line rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 84 T1s, 63 E1s, or 3 DS-3s.

• Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative protocols supported via HDLC termination and full packet store of the data within the HDLC structure.

MULTILINK PPP AND FRAME RELAY BUNDLES

• Capable of supporting fragment sizes from 1 to 9.6 Kbytes.

• Support for 3 egress fragmentation sizes (128, 256, and 512 bytes) configurable on a per multilink bundle. Optionally full packet transfers are supported on a per bundle basis.

• Supports up to 42 multilink bundles with up to 12 member links per bundle. These bundles are composed of independent HDLC channels.

• Support for up to 100ms of intra bundle skew in the receive direction when supporting the minimum fragment size.

• Support for PPP header compression as per RFC 1661.

PPP

• Support for 16 COS levels in accordance with RFC 2686.

• Either 12 bit or 24 bit sequence number, with short and long fragment header formats, is supported.

• Link Control protocol packets are identified by the PID as control protocols and will be forwarded to the Any-PHY interface.

FRAME RELAY

• Link layer address lookup can be performed based on HDLC channel and 10 bit DLCI for HDLC channels supporting Frame Relay protocols.

• The lookup algorithm can support a maximum of 16 K connection identifiers (CIs) amongst multilink FR bundles. The connection identifiers are ignored in singlelink FR channels.

• Control frames are identified and forwarded to Any-PHY interface.

• 12 bit sequence numbers supported.

• FECN, BECN, and DE ingress

HDLC

• Support for up to 1024 bidirectional HDLC channels, with individual HDLC channel speeds ranging from 56 Kbit/s to 52 Mbit/s. In a channelized application, the number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for E1).

• The 1024 HDLC channels can be assigned to a mixture of physical links via the 19.44 MHz SBI interface. The SBI transports the equivalent of 3 STS- 1 synchronous payload envelopes (SPE). Each STS-1 SPE can be individually configured to carry 28 T1/J1s, 21 E1s or 1 DS3.

• For each channel, supports programmable flag sequence detection and generation, bit stuffing and destuffing, and validation and generation of either CRC-CCITT or CRC-32 frame check sequences.

• For each channel, the receiver checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length.

APPLICATIONS

• IETF PPP interfaces for routers.

• Frame Relay interfaces for ATM or Frame Relay switches and multiplexers.

• Internet/Intranet access equipment.