DESCRIPTION

The PM73488 (QSE) is an advanced communications device that enables the implementation of high performance switching systems. The QSE is a 32 × 32 cell based switch element, with a total sustainable bandwidth of 5 Gb/s. (The peak, or raw, bandwidth is much more than that: about 8 Gb/s). The QSE is designed to be used with other QSE’s as part of a larger switch fabric. Various QSE combinations allow fabrics with theoretical peak capacities ranging from 5 Gb/s (one QSE) to 160 Gb/s. The QSE is not ATM specific; however, should the QSE be used for switching ATM cells, the QSE cell size is large enough to allow efficient direct mapping between QSE Cells and ATM cells.

FEATURES

Switching Algorithm

• Supports blocking resolution in the switch fabric.

• Guarantees a lower bound on switch performance using a patented randomization algorithm called Evil Twin Switching.

• Determines routes using specified bits in the header (self-routing switch fabric) for unicast traffic.

• Determines output groupings using a lookup table for multicast traffic.

• Allows output ports to be combined in groups of 1, 2, 4, 8, 16, or 32 for unicast traffic.

• Allows output ports to be combined in groups of 1, 2, or 4 for multicast traffic.

Multicast Support

• Supports optimal tree-based multicast replication in the switch fabric.

• Supports 512 internal multicast groups, expandable to 256K with external SRAM.

• Provides 64 internal cell buffers for multicast cells.

Diagnostic/Robustness Features

• Checks the header parity.

• Counts tagged cells.

• Checks for connectivity and stuck-at faults on all switch fabric interconnects.

I/O Features

• Provides 32 switch fabric interfaces with integrated phase aligner clock recovery circuitry.

• Provides a Start-Of-Cell (SOC) output per four switch element interfaces.

• Provides an external 8-bit Synchronous SRAM (SSRAM) interface for multicast group expansion.

• Provides a demultiplexed address/data CPU interface.

• Provides an IEEE 1149.1 (JTAG) boundary scan test bus.

Physical Characteristics

• 3.3 V supply voltage.

• 5 V tolerant inputs.

• 596-pin Enhanced Plastic Ball Grid Array (EPBGA) package.

• Operates from a single 66 MHz clock.