FEATURES

• Quad cell delineation block operating

up to a maximum rate of 52 Mbit/s.

• Provides a UTOPIA Level 2-

compatible ATM-PHY Interface.

• Implements the Physical Layer

Convergence Protocol (PLCP) for DS1

transmission systems according to the

ATM Forum User Network Interface

specification and ANSI TA-TSY-

000773, TA-TSY-000772, and E1

transmission systems according to the

ETSI 300-269 and ETSI 300-270.

• Supports SMDS PLCP and ATM Direct

Mapping into various rate transmission

systems in the following formats:

• E1 (2.048 Mbit/s) in CRC-4 and

PCM30;

• T1 (1.544 Mbit/s) in ESF and SF;

• Arbitrary Cell Rate (up to 52 Mbit/s)

with ATM Direct Mapping only.

• Uses the PMC-Sierra PM4341 T1XC,

PM4344 TQUAD, PM6341 E1XC, and

PM6344 EQUAD T1 and E1

framer/line interface chips for DS-1

and E1 applications.

• Provides programmable pseudorandom test pattern generation,

detection and analysis features.

• Provides performance monitoring

counters suitable for accumulation

periods of up to 1 second.

APPLICATIONS

• ATM Switches, Multiplexers, and Routers.

• SMDS Switches, Multiplexers and Routers.

• DSLAM.

• Integrated Access Devices (IAD).