DESCRIPTION

The PM7322 Routing Control, Monitoring and Policing 200 Mbps (RCMP-200) device is a monolithic integrated circuit that implements ATM layer functions that include fault and performance monitoring, header translation and cell rate policing. The RCMP-200 is intended to be situated between a switch core and the physical layer devices in the ingress direction. The RCMP-200 supports a sustained aggregate throughput of 0.355x106 cells/s. The RCMP-200 uses external SRAM to store per-VPI/VCI data structures. The device is capable of supporting up to 65536 connections.

FEATURES

• Monolithic single chip device which handles ATM switch Ingress VPI/VCI address translation, cell appending, cell rate policing, counting, and OAM requirements for 65,536 VCs (virtual circuits)

• Instantaneous transfer rate of 200 Mbit/s supports a cell transfer rate of 0.355x106 cells/s (one STS-3c).

• Concentrates the traffic from several PHY interfaces into one switch port.

• 8 bit PHY interface using direct addressing for up to 4 PHYs (compatible with Utopia Level 1 cell-level handshake) and Multi-PHY addressing for up to 32 PHYs (Utopia Level 2 compatible).

• 8 bit extended cell format SCI-PHY (52 - 64 byte extended ATM cell with prepend/postpend) interface at output to switch fabric.

• Compatible with wide range of switching fabrics and traffic management architectures including per VC or per PHY queuing.

• Provides identification/tagging of RM cells to support adjunct processing applications such as Virtual Source/Virtual Destination ABR service.

• Supports logical multicast.

• Flexible CAM-type cell identification which can use arbitrary VPI/VCI values and/or cell appended bytes for identification.

• Discards on command all low priority (high CLP bit) cells to relieve switch congestion.

• Can discard or tag the remainder of an AAL5 packet if a single cell in that packet is discarded or tagged due to policing.

• Includes a 16-bit FIFO buffered microprocessor bus interface for cell extraction and insertion (including OAM), VC table access, control and status monitoring, and configuration of the device.

• Supports DMA access for cell extraction and insertion.

• Uses common synchronous SRAMs for maintaining per-VC information.

• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.

• Provides a generic 16-bit microprocessor bus interface for configuration, control and status monitoring.

• Low power, 0.6 micron, +5 Volt CMOS technology.

• 240 copper slugged plastic quad flat pack (PQFP) package.

APPLICATIONS

• ATM Hubs and Workgroup Switches

• ATM Enterprise, Edge and Access Switches